The present invention relates to a pulse control circuit which is suitable for driving a capacitance load at high speed.
Reductions in the sustain voltage of elements which have resulted from the recent miniaturization of bipolar or MOS transistors have tended to reduce the operating voltages of integrated circuits. From the user's point of view, conventional supply voltages, such as supply voltages in units of 5 V, are desirable for ease of use. It is considered that means by which it will be possible to satisfy both the needs of the manufacturers of integrated circuits and the users is a reduction of the external supply voltage Vcc within the chips and the operation of miniaturized elements by a voltage V.sub.L which has been lowered thereby.
FIG. 1A is taken from U.S. patent application No. 368,162 applied for by the present Applicant. A miniaturized element 12a of FIG. 1B is used in an internal circuit a which determines the effective integration density of chips 10, and the remedy for the reduction in the voltage resistance resulting from miniaturization is to operate the element by a voltage V.sub.DP which is the external supply voltage Vcc reduced by a voltage limiter 30. However, it is usually easier to design a drive circuit b which uses a higher supply voltage and which includes, for example, an input-output interface, which does not contribute much to the integration density. Thus, a comparatively large element 12b, as shown in FIG. 1B, is used for the driving circuit b which is operated by applying Vcc thereto.
A chip is a single substrate on which memory, logic or other LSI devices are fabricated. In a memory LSI device, a from FIG. 1A is a memory array and its related circuits. On the other hand, in a logic LSI device, a is an area constructed of repeated cells making up the ROM or RAM area of a microcomputer. Details of embodiments of voltage limiters using this voltage limiter system are given in U.S. patent application Nos. 368,162 and 562,969.
When this kind of voltage limiter system is utilized for charging a capacitance load which has only a low voltage resistance in the circuit a, the output V.sub.DP of the voltage limiter 30 is supplied to the drain of a charging transistor as a supply voltage and, pulses of the same level as that of the external supply voltage Vcc are applied to the gate of the transistor, turning the transistor on.
In FIG. 2, a precharge circuit for a data line of a semiconductor memory is shown as an example of this type of circuit. In FIG. 2, charging transistors Q.sub.6, Q.sub.7 controlled by precharge pulse .phi..sub.P2 of a maximum level of Vcc charge data lines D.sub.o and D.sub.o to a voltage as large as the output voltage V.sub.DP of the voltage limiter 30. Numeral 1 denotes a memory cell array.
However, in this circuit, the equivalent internal resistance of the voltage limiter 30 is connected in series to the equivalent resistances of the charging transistors Q.sub.6 or Q.sub.7 when they are on, and thus it is necessary to make these resistances much smaller to enable charging at a higher speed when there is a larger capacitance load. For that purpose, the size of the transistors in the voltage limiter 30 and the transistors Q.sub.6, Q.sub.7 must be larger, and thus it can be understood that it is difficult to drive a large capacitance load faster when there must be a high degree of integration.